1. Field of the Invention
The present invention relates to an electronic circuit for switching the voltage applied to a memory circuit, and in particular to a method and apparatus for switching one of any number of voltage supplies with varying amplitudes to the wordlines of a Flash memory while providing isolation between the unswitched voltage supplies and the wordlines.
2. Description of the Prior Art
Common types of non-volatile memory, such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) and Flash memory use a charge on a memory cell's floating gate to control the threshold voltage (Vt) of the memory cell and thereby indicate the binary state of the cell. Typically, such memory cells have two possible binary states, one (e.g. "1") indicated by a high threshold voltage and one (e.g. "0") indicated by a low threshold voltage. Gathering electrons on a memory cell's floating gate increases the cell's threshold voltage and is referred to as writing or programming the memory cell. Erasing a memory cell removes the electrons from the floating gate and reduces the threshold voltage.
A Flash memory includes an array of electrically programmable and electrically erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor, which has the floating gate positioned between a control (input) gate and a channel located between the source and drain of the transistor. The threshold voltage Vt, adjusted by the charge stored on the floating gate, is the voltage that must be overcome by the gate to source voltage to activate the device.
For example, the threshold voltage Vt for a typical flash memory transistor with no charge stored on its floating gate is approximately one or two volts. This means that a voltage of at least two volts must be applied between the control gate and the source junction for the device to activate, that is, to allow current to flow through the device. The threshold voltage Vt for a typical flash memory transistor with charge stored on the floating gate is 6 volts. This means that a voltage of at least six volts must be applied between the control gate and the source junction for the device to activate, that is, to allow current to flow through the device.
The memory cells in the array are accessed via a plurality of column lines (digit lines) and a plurality of row lines (wordlines). Each of the wordlines is coupled to a control gate of a corresponding memory cell transistor. The activation of a cell, as noted above, occurs by supplying a voltage to the wordline to overcome the threshold voltage. The voltage level applied will depend upon the memory function desired, i.e. write, erase, read, etc. Thus, the write, erase, read and testing of a Flash memory chip requires that multiple voltages be supplied to the wordlines of the memory array at different times.
The multiple voltages necessary to be supplied to the Flash memory wordlines typically range from 1.5V to 7V. For example, Flash memory wordlines usually should be supplied with power supply voltage Vdd (3.3V) in a normal read operation, with 1.5-3.0V in a margin mode read operation and in a threshold voltage convergence after erase operation, and with 5.0-7.0V in a write operation. These voltages usually come from on-chip charge pumps or power supply pins such as Vdd.
Typically, a transistor circuit is used to control the switching of the multiple voltages to the Flash memory block wordlines and to provide isolation between each voltage supply and the wordlines biased at a higher or lower voltage by the other sources of voltage supply. An example of such a circuit is shown in FIG. 1.
Switching circuit 10 of FIG. 1 is used to switch voltage Vin1 12 or voltage Vin2 14 to a single output Vout 16. Voltages Vin1 12 and Vin2 14 are any two of the voltages used to control the functioning of the Flash memory block. The wordlines of the Flash memory block are connected to Vout 16. Transistors 20 and 22 are used as the switch transistors. The circuit is controlled by control signals PASS1 25 and PASS2 27, which are typically in the magnitude of 0V or 3.3V. The gate of transistor 20 is biased to either 0V or Vin1 12 by a level-shifter, which consists of level shifting circuit 35 and transistors 30, 31 which form an inverter. The gate of transistor 22 is biased to either 0V or Vout 16 by a second level-shifter, which consists of level shifting circuit 45 and transistors 40, 41 which form an inverter.
Suppose, for example, it is desired to switch voltage Vin1 12 to Vout 16. It will then also be necessary to suitably isolate Vin2 14 from Vout 16. In order to switch Vin1 12 to Vout 16, node N2 is set to 0V by control signal PASS1 25, level shifting circuit 35, and inverter formed by transistors 30, 31 in the following manner. Control signal PASS1 25 input to level shifting circuit 35 would be set to 3.3V. The signal output from level shifting circuit 35 at node N1 would be Vin 1 12. Transistor 30 would be off, and transistor 31 would be on, thus pulling node N2 to 0V. When node N2 is pulled to 0V, transistor 20 will turn on, thus switching Vin1 12 to Vout 16.
Simultaneously, Vout 16 is isolated from Vin2 14 by setting node N4 to Vout 16 by control signal PASS2 27, level shifting circuit 45 and transistors 40, 41 in the following manner. Control signal PASS2 27 input to level shifting circuit 45 would be set to 0V. The signal output from level shifting circuit 45 at node N3 would be 0V, thus turning on transistor 40 and turning off transistor 41. When transistor 40 is turned on, node N4 will be pulled up to Vout 16. When node N4 is pulled up to Vout 16, transistor 22 is turned off, thus isolating Vout 16 from Vin2 14. Thus, Vout 16 will carry the signal Vin1 12 and be isolated from Vin2 14.
A similar operation with the PASS1 25 and PASS2 27 voltages reversed would connect Vin2 14 to Vout 16 and isolate Vin1 12.